Electrostatic discharge (ESD) is a well-known problem. The problem of ESD continues to grow as integrated circuit dimensions continue to decrease. This ESD trend continues, especially with circuits having ultra-thin gate oxides. A conventional solution is to use direct ESD current shunting between VDD and VSS. FIG. 1 is a schematic diagram of a conventional ESD protection circuit 50. The ESD protection circuit 50 includes an input/output (I/O) protection circuit 60, which includes two diodes 62 and 64 coupled to an I/O pad 66, and a core power clamp 70, which includes a field effect transistor (FET) 72. In operation, generally, the ESD protection circuit 50 protects a circuit core 80 by shunting ESD current 82 caused by an ESD event 90 such as a voltage spike. The specific operation of the ESD protection circuit 50 is well known. The circuit core 80 is clocked with a system clock (not shown). The core power clamp 70 is referred as a “direct shunt,” because the FET 72 of the core power clamp 70 shunts the ESD current 82 directly from VDD to VSS. The shunting occurs when the FET 72 turns on, and the FET 72 turns on when the voltage at VDD exceeds a trigger voltage, or “snap-back voltage.” Such a voltage is caused by an ESD event. When the FET 72 turns on, it provides a low-resistance path for the ESD current 82 to be discharged from VDD to VSS.
FIG. 2 is a schematic diagram illustrating a voltage spike 92, which attenuates due to an inductance (L) impeding current 94 in the ESD protection circuit 50 of FIG. 1. A problem with the ESD protection circuit 50 is that localized voltage spikes can still damage some gate oxides. Voltage spikes 92 typically attenuate due an inductance (L) blocking current 94 at high frequency, which can occur during a charge device model (CDM) event. CDM is a form of ESD, and is well known. Because the inductance blocking current 94 occurs at a high frequency, the FET 72 cannot sense the attenuated voltage spike 92′ fast enough, if at all. As a result, some gate oxides in the circuit core 80 can still get damaged. The ESD protection circuit 50 is unable to prevent such failures.
Another problem with the ESD protection circuit 50 is that the ESD protection circuit 50 requires the FET 72 to be large enough to shunt sufficient current 82 away from the circuit core 80. Large FETs are undesirable, because large FETs take up a large amount of valuable space on a chip.
Another problem with the ESD protection circuit 50 is that if the operating voltage is lowered for low-power applications, the current sinking and voltage handling capabilities of the ESD protection circuit 50 are lowered. This is because the FET 72 switches more slowly when its operating voltage is lowered.
Accordingly, what is needed is an improved system and method for protecting a circuit from ESD. The system and method should be simple, cost effective and capable of being easily adapted to existing technology. The present invention addresses such a need.